april 2004 dsc-6435/0b 1 ? 2003 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. network search engine 32k x 72 entries datasheet brief 75n43102 device description idt provides proven, industry-leading network search engines (nses) that enable and accelerate the intelligent processing of network services in communications equipment. as a part of the complete idt classification subsystem that includes content inspection engines, the idt family of nses delivers high-performance, feature-rich, easy-to-use, integrated search accelerators. the idt 75n43102 is ideally suited for cost-sensitive applications in the enterprise and access markets. it is a full-ternary 32k x 72 entry device where each entry location in the nse has both a data entry and an associated mask entry. the nse devices integrate content addres- sable memory (cam) technology with high-performance logic. the device can perform lookup operations plus read and write maintenance operations. the idt 75n43102 nse device has a bi-directional bus that is a multiplexed address and data bus that can support 62.5 million sustained searches per second. this device can be configured to enable multiple width lookups from 72 to 288 bits wide. the idt 75n43102 requires a 1.5-volt v dd1 supply and a 2.5-volt v dd2 supply. the idt 75n43102 nse utilizes the latest high-performance 1.5v cmos processing technology and is packaged in a jedec standard, 256 pin low profile ball grid array. to request the full IDT75N43102 datasheet, please contact your local idt sales representative or call 1-831-754-4555 5346 drw02 figure 1.0 asic / fpga compatible nse network interface idt 75n43102 network search engine configuration registers clk2x ? cclk 2 configin matchin p r i o r i t y e n c o d e r s i z e l o g i c data d e c o d e address instruction matchout reqdata reqstb r/w 6435 drw 01 rst command bus phasen global mask registers request bus index bus configout 32k x 72 block diagram system configurations the idt nses are designed to fulfill the needs of various types of networking systems. in solutions requiring data searching such as routers, a system configuration as shown in figure 1.0 may be realized. in this compatible configuration, the nse interfaces directly to an asic/ fpga for lookups and routes an index directly back to the asic/ fpga. control of the associated handshake signals is provided by the nses for this configuration. asic or fpga
2 network search engine 32k x 72 entries datasheet brief 75n43102 registers there are three basic types of registers supported: n configuration registers are used at initialization to define the segmentation of the entries. n global mask registers are provided to support lookup instructions by masking individual bits during a search. n reply width registers are used with lookup operations. functional highlights figure 1.1 bus interface the nse utilizes a dual bus interface consisting of the nse request bus and the nse response bus. the nse request bus is comprised of the command bus and the request data bus. the command bus handles the instruction to the nse while the request data bus is the main data path to the nse. the 72 bit bi-directional request data bus functions as a multiplexed address and data bus, which performs the writing and reading of nse entries, as well as presenting lookup data to the device. the nse response bus is comprised of an independent unidirec- tional index bus which drives the result of the lookup (or index) to an asic. data and mask array the nse has data cell entries and associ- ated mask cell entries as shown in fig. 1.1. this combination of data and mask cell entries en- ables the nse to store 0, 1 or x, making it a full ternary network search engine. during a lookup operation, both arrays are used along with a global mask register to find a match to a requested data word. a6435 drw 03 data mask command bus the command bus loads the specific instructions into the nse. these include: n read or write a read or write instruction operates on a specified data entry, mask entry, or register. n lookup a lookup can be requested in 72-bit, 144-bit or 288-bit widths. a 36- bit lookup can be accomplished by using two global mask registers. features n n n n n full ternary 32k x 72 bit content addressable memory n n n n n global mask registers n n n n n 72/144/288 multiple width lookups n n n n n 62.5m sustained lookups per second at 72 and 144 width lookups n n n n n dual bus interface n n n n n cascadable to 2 devices with no glue logic or latency penalty n n n n n boundary scan jtag interface (ieee 1149.1compliant) n n n n n 1.5v match power supply n n n n n 2.5v core and i/o power supply
6.42 3 network search engine 32k x 72 entries datasheet brief 75n43102 signal descriptions pin function i/o description nse buses: request strobe input this input signifies a valid input request and signals the start of an nse operation cycle. command bus input this defines the instruction to be performed by the nse and selects a global mask register. request data bus input/output thre e state the request data bus is a multiplexed address/data bus used to perform reads (and writes) from (to) the nse, and to present search data for lookups. index bus output three state this bus is used to drive the lookup result information directly to the nse's asic/fpga. the index bus contains the encoded location at which the compare was found. clock and initialization: clock input input all inputs and outputs are referenced to the positive edge of this clock. clock phase enable input this signal is used to generate an internal clock at ? the frequency of the input clock. reset input this pin will force all outputs to a high impedence condition, as well as clearing the nse enable bit. depth expansion: configuration input configures the device id at power up. configuration output configures the device id at power up. match input input the match input signal is driven by the upstream match output signal. this indicates to the down stream nse that a hit in the higher priority nse has occurred. match output output the match output signal sig nifies that a match has occurred in the ns e. the signal is fed into the match input line of the lower priority nse. 6435 tbl 01
4 network search engine 32k x 72 entries datasheet brief 75n43102 revision history rev date p ages description 0 7/11/03 p.1-3 initial release a 08/14/03 p.4 updated pinout. b 04/12/04 all updated, removed pinout.
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